This invention relates to a sample-hold circuit, and more particularly to a sample-hold circuit used in a semiconductor device, such as, for example, a LCD (Liquid Crystal Display) driver for a liquid crystal television.
The LCD driver for liquid crystal television serves to sample video signals obtained by photographing to control lighting/non-lighting of respective liquid crystal elements in the LCD on the basis of sampled values. A sample-hold circuit used in such a LCD driver is of a structure including sample-hold elements provided respectively for those liquid crystal elements arranged in a matrix manner in the LCD, wherein the operation timings of respective sample-hold elements are shifted or delayed in sequence using outputs from respective stages of a shift register in order to shift timings at which those sample-hold elements sample video signals, in correspondence with shifts in respective scanning time points at the time of photographing.
FIG. 1 is a block diagram showing the configuration of a sample-hold circuit of this kind which has been developed for use in a LCD driver for a color liquid crystal television.
In the LCD for color liquid crystal television, liquid crystal elements 1Al, . . . , 1An and liquid crystal elements 1Bl, . . . , 1Bn, and liquid crystal elements 1Cl, . . . , 1Cn for respectively three primary color components A, B and C are interchangeably arranged as shown. For such liquid crystal elements 1Al, 1Bl, 1Cl, . . . , 1An, 1Bn, and 1Cn, sample-hold elements 2Al, 2Bl, 2Cl, . . . , 2An, 2Bn, and 2Cn for driving those elements are provided, respectively. These sample-hold elements are grouped according to colors of A, B and C of the liquid crystal elements for driving them. A group of elements 1Al, . . . , 1An are connected to a signal line 3A for a video signal V.sub.A of the color component A, a group of elements 1Bl, . . . , 1Bn are connected to a signal line 3B for a video signal V.sub.B of the color component B, and a group of elements 1Cl, . . . , 1Cn are connected to a signal line 3C of the video signal V.sub.C. Each sample-hold element is composed of an analog switch 4 for sampling video signals V.sub.A, V.sub.B or V.sub.C, a capacitor 5 for holding a sampled video signal, and a converter 6 for converting the video signal subjected to holding to a lighting/non-lighting control signal for the liquid crystal element to output it therefrom. It is to be noted that respective converters 6 concurrently carry out an output operation every each scanning line.
Since respective liquid crystal elements 1Al, 1Bl, 1Cl, . . . , 1An, 1Bn, 1Cn are positionally shifted at a predetermined pitch as shown, it is required to shift timings for sampling by respective sample-hold elements 2Al, 2Bl, 2Cl, . . . , 2An, 2Bn, 2Cn in correspondence with shifts of scanning time points at the time of photographing corresponding to those positional shifts. To realize this, three columns of n bit shift registers 7A, 7B and 7C respectively driven by clocks .phi..sub.A, .phi..sub.B and .phi..sub.C of three systems are provided. More particularly, outputs from the stages of the shift register 7A are connected to control terminals of analog switches 4 for sample-hold element group 1Al, . . . , 1An through a level shifter 8, respectively; outputs from the stages of the shift register 7B are connected to control terminals of analog switches 4 for the element group 1Bl, . . . , 1Bn through the level shifter 8, respectively; and outputs from the stages of the shift register 7C are connected to control terminals of analog switches 4 for sample-hold element group 1Cl, . . . , 1Cn through the level shifter 8, respectively. By the timing adjustment of clocks .phi..sub.A, .phi..sub.B and .phi..sub.C, the time points for shifting input Signals QA, QB and QC to respective stages of shift registers 7A, 7B and 7C of three columns are shifted or delayed every predetermined times. Thus, the sampling timings of respective sample-hold elements are shifted in sequence.
Such shift registers 7A, 7B and 7C employed in this embodiment may be n bit shift register of any structure in principle. It is a matter of course that an n bit shift register typically used from the past may be used. FIG. 2 shows a circuit diagram of one bit shift register constituting each stage of such a conventional typical n bit shift register. This one bit shift register 10 includes an input gate 11 comprised of a clocked inverter for taking a signal Q shifted from the preceding stage thereinto, an output gate comprised of a clocked inverter for shifting the signal Q thus taken in to the succeeding stage, and an external output line 13 for externally outputting the signal Q shifted from the output gate 12 to the succeeding stage.
The circuit configuration of the conventional n bit shift register thus constructed, which is used as the above-mentioned sample-hold circuit, is shown in FIG. 3. It is to be noted that only an extracted circuit section relevant to the video signal V.sub.A is shown in FIG. 3 for facility of understanding. The operation timing of the shift register in this circuit is shown in FIG. 4.
As shown in FIG. 3, output gates 12m, 12m+1, . . . of respective stages 10m, 10m+1, . . . of the shift register are placed in an on state in response to a rise of a reference clock .phi..sub.A serving as a reference for determining a sampling timing of the video signal V.sub.A, and are placed in an output hold state in response to its fall. In addition, input gates 11m, 11m+1, . . . are placed in an on state in response to a rise of a clock .phi..sub.A of the antiphase, and are placed in an output hold state in response to its fall. Thus, as shown in FIG. 4, for a time period from a rise to the next rise of the reference clodk .phi..sub.A, the output QAm of the m-th stage is maintained at a high level. For a subsequent time period from a rise to the next rise, the output QAm+1 of the (m+1)-th stage is maintained at a high level. For a further subsequent time period from a rise to the next rise, the output QAm+2 of the (m+2)-th stage is maintained at a high level. In a manner stated above, outputs of high level are shifted in succession to the succeeding stage every rises of the clock .phi..sub.A.
As shown in FIG. 3, interstage wiring capacity C corresponding to the wiring length exists in each connection lines between respective stages of the shift register. For this reason, the output waveforms of respective stages of the shift register shown in FIG. 4 have a time constant .tau. expressed by the equation .tau.=C.multidot.R where C represents the above-mentioned interstage wiring capacity and R represents an on resistance R of the output gate transistor. Accordingly, the output waveforms of the preceding and next stages of the shift register have an overlap at a portion transiently varying due to the time constant .tau.. In FIG. 4, this overlap portion is indicated by broken lines.
At this overlap portion, an analog switch (e.g., switch 4Am) driven by an output of the preceding stage shifts to off state, while an analog switch (e.g., switch 4Am+1) driven by an output of the next stage shifts to on state. For this reason, a noise produced when the analog switch 4Am+1 of the next stage is turned on is input through signal line 3A to the analog switch 4Am of the preceding stage which is being turned off. Thus, a voltage difference (offset) is produced between an input voltage V.sub.A delivered to the analog switch 4Am and a voltage VAm held by the capacitor 5Am.
Since such a sample-hold circuit is constructed in a folded manner as shown in FIG. 3 from a viewpoint of restriction of circuit space, the interstage connection line at the folded portion (e.g., between the (m+2)-th stage and (m+3)-th stage) becomes longer than those at other portions. For this reason, the interstage wiring capacity Cm+2 at the folded portion also becomes larger than those at other portions. As a result, the time constant .tau. of the output QAm+2 to which this capacity relates is prolonged. Accordingly, as shown in FIG. 4, the time period during which the output QAm+2 having a prolonged time constant and the output QAm+1 of the preceding stage overlap with each other becomes shorter than other overlap periods, while the time period during which this output QAm+2 and the output QAm+3 of the succeeding stage becomes longer than others. As a result, as shown in FIG. 5, hold voltages VAm, VAm+1, . . . of respective sample-hold elements would produce offset variations. Such variations cause noise in the form of a longitudinal stripe or interdigital noise on a television screen driven by hold voltages.